Coding and decoding of a polar code concatenated with interleaving with an outer systematic code

ABSTRACT

Systems and methods related to concatenated polar encoding with interleaving are disclosed. In some embodiments, a method of operation of a radio node to perform encoding of a plurality of data bits for transmission by the radio node comprises encoding a plurality of data bits using a linear encoder to provide a first plurality of coded bits, where the first plurality of coded bits comprises a plurality of parity bits and the plurality of data bits. The method further comprises interleaving the first plurality of coded bits in accordance with an interleaving mapping to provide a plurality of interleaved bits and encoding the plurality of interleaved bits using a polar encoder to provide a second plurality of coded bits to be transmitted by the radio node.

RELATED APPLICATIONS

The present application is a continuation of U.S. application Ser. No.16/261,731, filed Jan. 30, 2019, which is a continuation ofInternational Application No. PCT/IB2017/058082, filed Dec. 18, 2017,which claims priority to Provisional Application No. 62/444,560 filedJan. 10, 2017, the disclosures of which are incorporated herein byreference in their entireties.

TECHNICAL FIELD

Embodiments of the present disclosure relate to the field of wirelesscommunication, and more specifically to methods, an apparatus, andsystems for implementing concatenated polar code with interleaving.

BACKGROUND

Polar codes, proposed by Arikan [1], are the first class of constructivecoding schemes that are provable to achieve the symmetric capacity ofthe binary-input discrete memoryless channels under a low-complexitySuccessive Cancellation (SC) decoder. However, the finite-lengthperformance of polar codes under SC is not competitive compared to othermodern channel coding schemes such as Low-Density Parity-Check (LDPC)codes and turbo codes. Later, a SC List (SCL) decoder is proposed in[2], which can approach the performance of optimal Maximum-Likelihood(ML) decoder. By concatenating a simple Cyclic Redundancy Check (CRC)coding, it was shown that the performance of concatenated polar code iscompetitive with that of well-optimized LDPC and turbo codes. As aresult, polar codes are being considered as a candidate for future FifthGeneration (5G) wireless communication systems.

The main idea of polar coding is to transform a pair of identicalbinary-input channels into two distinct channels of different qualities,one better and one worse than the original binary-input channel. Byrepeating such a pair-wise polarizing operation on a set of 2^(M)independent uses of a binary-input channel, a set of 2^(M)“bit-channels” of varying qualities can be obtained. Some of these bitchannels are nearly perfect (i.e., error free) while the rest of the bitchannels are nearly useless (i.e., totally noisy). The point is to usethe nearly perfect channel to transmit data to the receiver whilesetting the input to the useless channels to have fixed or frozen values(e.g., 0) known to the receiver. For this reason, those input bits tothe nearly useless and the nearly perfect channel are commonly referredto as frozen bits and non-frozen (or information) bits, respectively.Only the non-frozen bits are used to carry data in a polar code. Anillustration of the structure of a length-8 polar code is illustrated inFIG. 1.

Although the original polar code, as proposed by Arikan [1], was provento be capacity achieving with a low-complexity SC decoder, thefinite-length performance of polar codes under SC is not competitivecompared to other modern channel coding schemes such LDPC and turbocodes. A more complex decoder, namely the SCL decoder, is proposed in[2], where a list of more than one surviving decision path is maintainedin the decoding process, but the resulting performance is stillunsatisfactory. In [2], it was further proposed that by concatenating alinear outer code, namely a CRC code, with the original polar code asinner code, the outer code can be used to check if any of the candidatepaths in the list are correctly decoded. Such a two-step decodingprocess significantly improves the performance and makes polar codescompetitive with that of well-optimized LDPC and Turbo codes. However,such a two-step decoding process is in general sub-optimal as each stepdoes not take into the account of the structure of the other (inner orouter) code.

SUMMARY

Systems and methods related to concatenated polar encoding withinterleaving are disclosed. In some embodiments, a method of operationof a radio node to perform encoding of a plurality of data bits fortransmission by the radio node comprises encoding a plurality of databits using a linear encoder to provide a first plurality of coded bits,where the first plurality of coded bits comprises a plurality of paritybits and the plurality of data bits. The method further comprisesinterleaving the first plurality of coded bits in accordance with aninterleaving mapping to provide a plurality of interleaved bits andencoding the plurality of interleaved bits using a polar encoder toprovide a second plurality of coded bits to be transmitted by the radionode. In some embodiments, this concatenated polar encoding withinterleaving of the data and parity bits enables single-step decoding atthe receiver. In some embodiments, the interleaving of the data andparity bits enables the bit-wise checking of the parity bits earlier inthe decoding process, which in turn reduces the latency of the decodingprocess.

In some embodiments, the interleaving mapping maps the plurality ofinterleaved bits to inputs of the polar encoder.

In some embodiments, the plurality of interleaved bits is a sequence ofbits comprising the plurality of parity bits interleaved with theplurality of data bits, and the interleaving mapping is such that atleast one of the plurality of parity bits precedes at least one of theplurality of data bits in the sequence of bits.

In some embodiments, the plurality of interleaved bits is a sequence ofbits comprising the plurality of parity bits interleaved with theplurality of data bits and each parity bit of the plurality of paritybits is a function of a respective subset of the plurality of data bits.Further, the interleaving mapping is such that at least one of theplurality of parity bits is at a position in the sequence of bits thatis: (a) after all of the subset of the plurality of data bits of whichthe at least one of the plurality of parity bits is a function and (b)before a last of the plurality of data bits within the sequence of bits.

In some embodiments, the plurality of interleaved bits is a sequence ofbits comprising the plurality of parity bits interleaved with theplurality of data bits and each parity bit of the plurality of paritybits is a function of a respective subset of the plurality of data bits.Further, the interleaving mapping is such that at least one of theplurality of parity bits is at a position in the sequence of bits thatis: (a) immediately after a last of the subset of the plurality of databits of which the at least one of the plurality of parity bits is afunction within the sequence of bits and (b) before a last of theplurality of data bits within the sequence of bits.

In some embodiments, encoding the plurality of data bits using thelinear encoder comprises encoding the plurality of data bits inaccordance with a generator matrix G_(outer)=[I|P_(outer)], where I isan identity matrix of size K×K where K is the number of data bits in theplurality of data bits and P_(outer) is a parity matrix that defineseach of the plurality of parity bits as a function of a respectivesubset of the plurality of data bits. Further, the interleaving mappingis defined as ϕ=b∘ϕ_(c), where b is a bit mapping that maps theplurality of interleaved bits to a plurality of non-frozen inputs of thepolar encoder and ϕ_(c) is a column permutation mapping of a columnpermutation matrix Φ_(c) that, together with a row permutation matrixΦ_(r), provide G′_(outer)

Φ_(r)G_(outer)Φ_(c) ^(T), where G′_(outer) is an upper block-triangularmatrix with exactly K being those of the identity matrix I.

In some embodiments, the linear encoder is a Cyclic Redundancy Check(CRC) encoder.

Embodiments of a radio node for performing encoding of a plurality ofdata bits for transmission by the radio node are also disclosed. In someembodiments, a radio node for performing encoding of a plurality of databits for transmission by the radio node is adapted to encode a pluralityof data bits using a linear encoder to provide a first plurality ofcoded bits, where the first plurality of coded bits comprises aplurality of parity bits and the plurality of data bits. The radio nodeis further adapted to interleave the first plurality of coded bits inaccordance with an interleaving mapping to provide a plurality ofinterleaved bits and encode the plurality of interleaved bits and one ormore frozen bits using a polar encoder to provide a second plurality ofcoded bits to be transmitted by the radio node.

In some embodiments, a radio node for performing encoding of a pluralityof data bits for transmission by the radio node comprises a transmitterand at least one processor operable to encode a plurality of data bitsusing a linear encoder to provide a first plurality of coded bits, wherethe first plurality of coded bits comprises a plurality of parity bitsand the plurality of data bits. The at least one process is furtheroperable to interleave the first plurality of coded bits in accordancewith an interleaving mapping to provide a plurality of interleaved bitsand encode the plurality of interleaved bits and one or more frozen bitsusing a polar encoder to provide a second plurality of coded bits to betransmitted by the radio node.

In some embodiments, the interleaving mapping maps the plurality ofinterleaved bits to inputs of the polar encoder.

In some embodiments, the plurality of interleaved bits is a sequence ofbits comprising the plurality of parity bits interleaved with theplurality of data bits, and the interleaving mapping is such that atleast one of the plurality of parity bits precedes at least one of theplurality of data bits in the sequence of bits.

In some embodiments, the plurality of interleaved bits is a sequence ofbits comprising the plurality of parity bits interleaved with theplurality of data bits and each parity bit of the plurality of paritybits is a function of a respective subset of the plurality of data bits.Further, the interleaving mapping is such that at least one of theplurality of parity bits is at a position in the sequence of bits thatis: (a) after all of the subset of the plurality of data bits of whichthe at least one of the plurality of parity bits is a function and (b)before a last of the plurality of data bits within the sequence of bits.

In some embodiments, the plurality of interleaved bits is a sequence ofbits comprising the plurality of parity bits interleaved with theplurality of data bits, and each parity bit of the plurality of paritybits is a function of a respective subset of the plurality of data bits.Further, the interleaving mapping is such that at least one of theplurality of parity bits is at a position in the sequence of bits thatis: (a) immediately after a last of the subset of the plurality of databits of which the at least one of the plurality of parity bits is afunction within the sequence of bits and (b) before a last of theplurality of data bits within the sequence of bits.

In some embodiments, in order to encode the plurality of data bits usingthe linear encoder, the radio node is further operable to encode theplurality of data bits in accordance with a generator matrixG_(outer)=[I|P_(outer)], where I is an identity matrix of size K×K whereK is the number of data bits in the plurality of data bits and P_(outer)is a parity matrix that defines each of the plurality of parity bits asa function of a respective subset of the plurality of data bits.Further, the interleaving mapping is defined as ϕ=b∘ϕ_(c), where b is abit mapping that maps the plurality of interleaved bits to a pluralityof non-frozen inputs of the polar encoder, and ϕ_(c) is a columnpermutation mapping of a column permutation matrix Φ_(c) that, togetherwith a row permutation matrix Φ_(r), provide G′_(outer)

Φ_(r)G_(outer)Φ_(c) ^(T), where G′_(outer) is an upper block-triangularmatrix with exactly K being those of the identity matrix I.

In some embodiments, the linear encoder is a CRC encoder.

Embodiments of a method of operation of a radio node to perform decodingof a plurality of coded bits received by the radio node are alsodisclosed. In some embodiments, a method of operation of a radio node toperform decoding of a plurality of coded bits received by the radio nodecomprises decoding a plurality of coded data bits using a polar decoderto provide a plurality of decoded bits, where the plurality of decodedbits comprises a plurality of parity bits interleaved with a pluralityof data bits. The method further comprises deinterleaving the pluralityof decoded bits in accordance with an interleaving mapping to therebyprovide the plurality of parity bits and the plurality of data bits.

In some embodiments, decoding the plurality of coded bits comprisesdecoding a plurality of input Log-Likelihood Ratios (LLRs) of theplurality of coded bits using a modified Successive Cancellation List(SCL) polar decoder, wherein the plurality of coded bits is a pluralityof polar encoded bits that result from a polar encoding of the pluralityof interleaved bits comprising the plurality of data bits and theplurality of parity bits that are interleaved with the plurality of databits in accordance with the interleaving mapping and the modified SCLpolar decoder is a SCL polar decoder that takes into account theinterleaving mapping.

In some embodiments, the plurality of interleaved bits is a sequence ofbits comprising the plurality of parity bits interleaved with theplurality of data bits, and the interleaving mapping is such that atleast one of the plurality of parity bits precedes at least one of theplurality of data bits in the sequence of bits.

In some embodiments, the plurality of interleaved bits is a sequence ofbits comprising the plurality of parity bits interleaved with theplurality of data bits and each parity bit of the plurality of paritybits is a function of a respective subset of the plurality of data bits.Further, the interleaving mapping is such that at least one of theplurality of parity bits is at a position in the sequence of bits thatis: (a) after all of the subset of the plurality of data bits of whichthe at least one of the plurality of parity bits is a function and (b)before a last of the plurality of data bits within the sequence of bits.

In some embodiments, the plurality of interleaved bits is a sequence ofbits comprising the plurality of parity bits interleaved with theplurality of data bits and each parity bit of the plurality of paritybits is a function of a respective subset of the plurality of data bits.Further, the interleaving mapping is such that at least one of theplurality of parity bits is at a position in the sequence of bits thatis: (a) immediately after a last of the subset of the plurality of databits of which the at least one of the plurality of parity bits is afunction within the sequence of bits and (b) before a last of theplurality of data bits within the sequence of bits.

In some embodiments, the plurality of data bits and the plurality ofparity bits are a result of CRC encoding of the plurality of data bits.

Embodiments of a radio node to perform decoding of a plurality of codedbits received by the radio node are also disclosed. In some embodiments,a radio node to perform decoding of a plurality of coded bits receivedby the radio node is adapted to decode a plurality of coded data bitsusing a polar decoder to provide a plurality of decoded bits, where theplurality of decoded bits comprising a plurality of parity bitsinterleaved with a plurality of data bits. The radio node is furtheradapted to deinterleave the plurality of decoded bits in accordance withan interleaving mapping to thereby provide the plurality of parity bitsand the plurality of data bits.

In some embodiments, a radio node to perform decoding of a plurality ofcoded bits received by the radio node comprises a transmitter and atleast one processor operable to decode a plurality of coded data bitsusing a polar decoder to provide a plurality of decoded bits, where theplurality of decoded bits comprises a plurality of parity bitsinterleaved with a plurality of data bits, and deinterleave theplurality of decoded bits in accordance with an interleaving mapping tothereby provide the plurality of parity bits and the plurality of databits.

In some embodiments, in order to decode the plurality of coded bits, theat least one processor is further operable to decode a plurality ofinput LLRs of the plurality of coded bits using a modified SCL polardecoder, wherein the plurality of coded bits is a plurality of polarencoded bits that result from a polar encoding of the plurality ofinterleaved bits comprising the plurality of data bits and the pluralityof parity bits that are interleaved with the plurality of data bits inaccordance with the interleaving mapping and the modified SCL polardecoder is a SCL polar decoder that takes into account the interleavingmapping.

In some embodiments, the plurality of interleaved bits is a sequence ofbits comprising the plurality of parity bits interleaved with theplurality of data bits, and the interleaving mapping is such that atleast one of the plurality of parity bits precedes at least one of theplurality of data bits in the sequence of bits.

In some embodiments, the plurality of interleaved bits is a sequence ofbits comprising the plurality of parity bits interleaved with theplurality of data bits and each parity bit of the plurality of paritybits is a function of a respective subset of the plurality of data bits.Further, the interleaving mapping is such that at least one of theplurality of parity bits is at a position in the sequence of bits thatis: (a) after all of the subset of the plurality of data bits of whichthe at least one of the plurality of parity bits is a function and (b)before a last of the plurality of data bits within the sequence of bits.

In some embodiments, the plurality of interleaved bits is a sequence ofbits comprising the plurality of parity bits interleaved with theplurality of data bits and each parity bit of the plurality of paritybits is a function of a respective subset of the plurality of data bits.Further, the interleaving mapping is such that at least one of theplurality of parity bits is at a position in the sequence of bits thatis: (a) immediately after a last of the subset of the plurality of databits of which the at least one of the plurality of parity bits is afunction within the sequence of bits and (b) before a last of theplurality of data bits within the sequence of bits.

In some embodiments, the plurality of data bits and the plurality ofparity bits are a result of CRC encoding of the plurality of data bits.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawing figures incorporated in and forming a part ofthis specification illustrate several aspects of the disclosure, andtogether with the description serve to explain the principles of thedisclosure.

FIG. 1 is an example of a polar code structure with N=8, according tovarious embodiments of the present disclosure;

FIG. 2 illustrates one example of a cellular communications networkaccording to some embodiments of the present disclosure;

FIG. 3 is an illustration of an encoder structure of an interleavedconcatenated polar code, according to an embodiment of the presentdisclosure;

FIG. 4 is a flow chart that illustrates the operation of the encoderstructure of FIG. 3 according to some embodiments of the presentdisclosure;

FIG. 5 is an Illustration of a one-step decoder structure for aninterleaved concatenated polar code, according to an embodiment of thepresent disclosure;

FIG. 6 is a flow chart that illustrates the operation of the decoderstructure of FIG. 5 according to some embodiments of the presentdisclosure;

FIG. 7 is a flow diagram of a design of an interleaver, according to anexemplary embodiment of the present disclosure;

FIG. 8 is an exemplary block diagram of a radio access node, accordingto various exemplary embodiments of the present disclosure;

FIG. 9 is an exemplary block diagram of an embodiment of a radio accessnode, according to various embodiments of the present disclosure;

FIG. 10 is a diagram of an exemplary virtualized radio access node,according to various embodiments described herein;

FIG. 11 is a block diagram of an exemplary User Equipment device (UE),according to various embodiments described herein; and

FIG. 12 is a block diagram of an exemplary UE, according to variousembodiments described herein.

DETAILED DESCRIPTION

The embodiments set forth below represent information to enable thoseskilled in the art to practice the embodiments and illustrate the bestmode of practicing the embodiments. Upon reading the followingdescription in light of the accompanying drawing figures, those skilledin the art will understand the concepts of the disclosure and willrecognize applications of these concepts not particularly addressedherein. It should be understood that these concepts and applicationsfall within the scope of the disclosure.

In the following description, numerous specific details are set forth.However, it is understood that embodiments of the present disclosure maybe practiced without these specific details. In other instances,well-known circuits, structures, and techniques have not been shown indetail in order not to obscure the understanding of this description.Those of ordinary skill in the art, with the included descriptions, willbe able to implement appropriate functionality without undueexperimentation.

References in the specification to “one embodiment,” “an embodiment,”“an example embodiment,” etc., indicate that the embodiment describedmay include a particular feature, structure, or characteristic, butevery embodiment may not necessarily include the particular feature,structure, or characteristic. Moreover, such phrases are not necessarilyreferring to the same embodiment. Further, when a particular feature,structure, or characteristic is described in connection with anembodiment, it is submitted that it is within the knowledge of oneskilled in the art to implement such feature, structure, orcharacteristic in connection with other embodiments whether or notexplicitly described.

In the following description and claims, the terms “coupled” and“connected,” along with their derivatives, may be used. It should beunderstood that these terms are not intended as synonyms for each other.“Coupled” is used to indicate that two or more elements, which may ormay not be in direct physical or electrical contact with each other,co-operate or interact with each other. “Connected” is used to indicatethe establishment of communication between two or more elements that arecoupled with each other.

The embodiments set forth below represent information to enable thoseskilled in the art to practice the embodiments and illustrate the bestmode of practicing the embodiments. Upon reading the followingdescription in light of the accompanying drawing figures, those skilledin the art will understand the concepts of the disclosure and willrecognize applications of these concepts not particularly addressedherein. It should be understood that these concepts and applicationsfall within the scope of the disclosure.

Radio Node: As used herein, a “radio node” is either a radio access nodeor a wireless device.

Radio Access Node: As used herein, a “radio access node” is any node ina radio access network of a cellular communications network thatoperates to wirelessly transmit and/or receive signals. Some examples ofa radio access node include, but are not limited to, a base station(e.g., an enhanced or evolved Node B (eNB) in a Third GenerationPartnership Project (3GPP) Long Term Evolution (LTE) network or a FifthGeneration (5G) New Radio (NR) base station, which is referred to as agNB), a high-power or macro base station, a low-power base station(e.g., a micro base station, a pico base station, a home eNB, or thelike), and a relay node.

Core Network Node: As used herein, a “core network node” is any type ofnode in a core network. Some examples of a core network node include,e.g., a Mobility Management Entity (MME), a Packet Data Network Gateway(P-GW), a Service Capability Exposure Function (SCEF), or the like.

Wireless Device: As used herein, a “wireless device” is any type ofdevice that has access to (i.e., is served by) a cellular communicationsnetwork by wirelessly transmitting and/or receiving signals to a radioaccess node(s). Some examples of a wireless device include, but are notlimited to, a User Equipment device (UE) in a 3GPP network and a MachineType Communication (MTC) device.

Network Node: As used herein, a “network node” is any node that iseither part of the radio access network or the core network of acellular communications network/system.

Note that the description given herein focuses on a 3GPP cellularcommunications system and, as such, 3GPP LTE or NR terminology orterminology similar to 3GPP LTE or NR terminology is oftentimes used.However, the concepts disclosed herein are not limited to LTE, NR, or a3GPP system.

As disclosed herein, methods, systems and apparatus are disclosed foradding a bit-interleaver between a linear outer code (e.g., the CyclicRedundancy Check (CRC) code) and a polar inner code. Such an interleaverallows some of the parity bits generated by the outer code to be usedearlier to positively influence the decisions made in a modifiedSuccessive Cancellation List (SCL) decoder for the polar inner code.According to an exemplary advantage, this allows a single-step decodingfor the overall concatenated code while outperforming its two-stepcounterpart.

As described herein, the design of the interleaver can be achieved byrow and column permutations of a systematic generating matrix of thelinear outer code. Given the resulting interleaving mapping, a modifiedSCL decoder can decode the inner polar code while taking into accountthe parity bits generated by the linear outer code.

According to various embodiments, an advantage of features herein is toenable a single-step decoding process for the concatenation of anylinear outer code and a polar inner code through a judicious design ofthe interleaver, as opposed to a two-step decoding process where theinner polar code is first decoded followed by the decoding of the outercode. Such a single-step decoding jointly takes into account thestructure of the polar inner code and the linear outer code and thusimproves the performance, compared to the two-step solution. It alsoreduces the amount of interfacing needed in hardware and thus theoverall decoding latency.

In addition, CRC checking can be done bit-by-bit for each individual CRCbit. This is in contrast to existing methods where the entirelength-K_(CRC) vector of CRC bits are used in CRC checking, whereK_(CRC) denotes the number of parity bits or CRC bits generated by theCRC code.

The CRC checking can be performed during the SCL decoding. This is incontrast to existing methods which performs CRC checking only at the endof SCL decoding.

Various other features and advantages will become obvious to one ofordinary skill in the art in light of the following detailed descriptionand drawings.

FIG. 2 illustrates one example of a cellular communications network 200according to some embodiments of the present disclosure. In theembodiments described herein, the cellular communications network 200 isa 5G NR network. In this example, the cellular communications network200 includes base stations 202-1 and 202-2, which in LTE are referred toas eNBs and in 5G NR are referred to as gNBs, controlling correspondingmacro cells 204-1 and 204-2. The base stations 202-1 and 202-2 aregenerally referred to herein collectively as base stations 202 andindividually as base station 202. Likewise, the macro cells 204-1 and204-2 are generally referred to herein collectively as macro cells 204and individually as macro cell 204. The cellular communications network200 also includes a number of low power nodes 206-1 through 206-4controlling corresponding small cells 208-1 through 208-4. The low powernodes 206-1 through 206-4 can be small base stations (such as pico orfemto base stations) or Remote Radio Heads (RRHs), or the like. Notably,while not illustrated, one or more of the small cells 208-1 through208-4 may alternatively be provided by the base stations 202. The lowpower nodes 206-1 through 206-4 are generally referred to hereincollectively as low power nodes 206 and individually as low power node206. Likewise, the small cells 208-1 through 208-4 are generallyreferred to herein collectively as small cells 208 and individually assmall cell 208. The base stations 202 (and optionally the low powernodes 206) are connected to a core network 210.

The base stations 202 and the low power nodes 206 provide service towireless devices 212-1 through 212-5 in the corresponding cells 204 and208. The wireless devices 212-1 through 212-5 are generally referred toherein collectively as wireless devices 212 and individually as wirelessdevice 212. The wireless devices 212 are also sometimes referred toherein as UEs.

Various network nodes can perform the functionality described below. Forexample, an access node (e.g., an eNB or gNB), such as the base station202 or 206, could perform the various interleaving steps providedherein. One of ordinary skill in the art would realize that a receiver(e.g., a receiver at a wireless device 212 or UE) would be able toperform the corresponding decoding, according to one example. Of course,it would be readily understood by one of ordinary skill in the art thatvarious combinations of radio nodes could be implemented to perform thefunctionality described herein.

Various embodiments described herein are directed to adding ajudiciously designed interleaver between the concatenation of a linearouter code and a polar inner code such that a single-pass or single-stepdecoding can be done using a slightly modified SCL polar decoder tojointly exploit the structure of both the inner and outer coder. Such aninterleaver allows some of the parity bits generated by the outer codeto be used earlier to positively influence the decisions made in amodified SCL decoder for the polar inner code. This allows a single-stepdecoding for the overall concatenated code while outperforming itstwo-step counterpart.

Since the interleaver may be an important aspect of features herein,details are also provided on how the design of the interleaver can beachieved by row and column permutations of a systematic generatingmatrix of the linear outer code.

According to an embodiment, an interleaver can be added between a linearouter code, such as a CRC code, and a polar inner code to facilitatelist decoding for the inner polar code that takes into account thedependency structure of the parity bits and the data bits from the outercode. The encoder structure of the overall proposed code is illustratedin FIG. 3.

In this regard, FIG. 3 illustrates an interleaved concatenated polarencoder 300 in accordance with some embodiments of the presentdisclosure. The interleaved concatenated polar encoder 300 isimplemented at a radio node such as, e.g., a base station 202 or 204 ora wireless device 212. As illustrated, the interleaved concatenatedpolar encoder 300 includes a linear (outer) encoder 302, an interleaver304, and a polar (inner) encoder 306. The linear encoder 302, theinterleaver 304, and the polar encoder 306 may be implemented inhardware or a combination of hardware and software, as will beappreciated by one of ordinary skill in the art.

As shown in FIG. 3, the information-carrying data bits u (also referredto herein as data bits u) are first encoded by a linear outer code togenerate some outer parity bits p_(outer) along with the data bits u.All these bits x_(outer)=[u|p_(outer)] are interleaved and put into thepolar (inner) encoder 306 along with the frozen bits to generate theoverall coded bits x. The interleaver 304 operates based on apredetermined interleaving mapping ϕ(⋅).

FIG. 4 is a flow chart that illustrates the operation of the interleavedconcatenated polar encoder 300 of FIG. 3. This flow chart corresponds tothe description of the operation of the interleaved concatenated polarencoder 300 provided above. As illustrated, the interleaved concatenatedpolar encoder 300 encodes the data bits u using the linear encoder 302to provide first coded bits (x_(outer)) (step 400). As discussed herein,in some embodiments, the linear (outer) encoder 302 is a CRC encoder.The first coded bits (x_(outer)) form a sequence of bits that is aconcatenation of the data bits (u) and a number of parity bits(p_(outer)) (i.e., x_(outer)=[u|p_(outer)]). The interleaver 304interleaves the first coded bits (x_(outer)), and in particularinterleaves the parity bits (p_(outer)) with the data bits (u) inaccordance with the interleaving mapping ϕ(⋅), to provide interleavedbits (step 402). As discussed herein, the interleaving mapping ϕ(⋅)interleaves the parity bits (p_(outer)) with the data bits (u) and mapsthe resulting interleaved bits to the non-frozen inputs of the polarencoder 306. The polar encoder 306 then performs polar encoding of theinterleaved bits and a number of frozen bits to provide the coded bits(x) (step 404).

As described herein, the interleaved bits are a sequence of bitscomprising the parity bits (p_(outer)) interleaved with the data bits(u), where the interleaving mapping ϕ(⋅) is such that at least one ofthe parity bits precedes at least one of the data bits in this sequenceof bits. As also described herein, in some embodiments, each parity bitis a function of a respective subset of the data bits (u), and theinterleaving mapping ϕ(⋅) is such that at least one of the parity bitsis at a position in the interleaved sequence of bits that is: (a) afterall of the subset of the data bits of which the parity bit is a functionand (b) before a last of the data bits in the interleaved sequence ofbits. As also described herein, in some embodiments, each parity bit isa function of a respective subset of the data bits (u), and theinterleaving mapping ϕ(⋅) is such that at least one of the parity bitsis at a position in the interleaved sequence of bits that is: (a)immediately after a last of the subset of the data bits of which theparity bit is a function within the interleaved sequence of bits and (b)before a last of the data bits in the interleaved sequence of bits. Bypositioning the parity bits within the interleaved sequence of bits inthis manner, during decoding, at least some of the parity bits can bedecoded before the last of the data bits is decoded and therefore usedto positively influence the decoding process (e.g., by continuing on aparticular branch of the SCL decoding process if a decoded parity bit iscorrect or discontinuing the particular branch of the SCL decodingprocess if the decoded parity bit is incorrect).

As also described below in detail, in some embodiments, encoding thedata bits (u) using the linear encoder 302 includes encoding the databits (u) using the linear encoder 302 in accordance with a generatormatrix G_(outer)=[I|P_(outer)], where I is an identity matrix of sizeK×K where K is the number of data bits in the plurality of data bits andP_(outer) is a parity matrix that defines each of the plurality ofparity bits as a function of a respective subset of the plurality ofdata bits. Further, the interleaving mapping ϕ(⋅) is defined asϕ=b∘ϕ_(c), where b is a bit mapping that maps the plurality ofinterleaved bits to the plurality of non-frozen inputs of the polarencoder and ϕ_(c) is a column permutation mapping of a columnpermutation matrix Φ_(c) that, together with a row permutation matrixΦ_(r), provide G′_(outer)

Φ_(r)G_(outer)Φ_(c) ^(T), where G′_(outer) is an upper block-triangularmatrix with exactly K being those of the identity matrix I.

While FIGS. 3 and 4 focus on the operation of the interleavedconcatenated polar encoder 300 at the transmitter, FIGS. 5 and 6describe a one-step decoder 500 and the operation thereof at thereceiver. At the receiver, the structure of the one-step decoder 500 isillustrated in FIG. 5, where the input Log-Likelihood Ratios (LLRs) y ofthe coded bits are first decoded using a modified SCL polar decoder 502,whose outputs are then passed through a deinterleaver 504 that extractthe decoded data bits u. The deinterleaver 504 depends on theinterleaving mapping ϕ(⋅) used in the interleaved concatenated polarencoder 300. The operations of the modified SCL polar decoder 502 aresimilar to an ordinary SCL polar decoder except that whenever an outerparity bit is reached, as indicated by the interleaving mapping ϕ(⋅),during the successive decoding process, its value is computed based onthe previous data bits as indicated by the corresponding columns of thegenerating matrix of the outer code.

FIG. 6 is a flow chart that illustrates the operation of the one-stepdecoder 500 of FIG. 5. This flow chart corresponds to the description ofthe operation of the one-step decoder 500 provided above. Asillustrated, the one-step decoder 500 (optionally) obtains LLRs of thecoded bits (e.g., in the conventional manner) (step 600). The modifiedSCL polar decoder 502 decodes the LLRs of the coded bits to providesdecoded bits (step 602). The coded bits are polar encoded bits thatresult from polar encoding of interleaved bits including data bits (u)and parity bits (p_(outer)) interleaved with the data bits (u) inaccordance with the interleaving mapping ϕ(⋅), as described above. Themodified SCL polar decoder 502 is a SCL polar decoder that takes intoaccount the interleaving mapping ϕ(⋅). More specifically, as discussedabove, the operations of the modified SCL polar decoder 502 are similarto an ordinary SCL polar decoder except that whenever an outer paritybit is reached, as indicated by the interleaving mapping ϕ(⋅), duringthe successive decoding process, its value is computed based on theprevious data bits as indicated by the corresponding columns of thegenerating matrix of the outer code.

The decoded bits include the parity bits (p_(outer)) interleaved withthe data bits (u). As such, the deinterleaver 504 deinterleaves the databits (u) and the parity bits (p_(outer)) (step 604).

A description of the design of the interleaver 304 and, in particularthe interleaving mapping ϕ(⋅), in accordance with some embodiments ofthe present disclosure will now be provided. A generic procedure isdescribed herein for designing the interleaving mapping ϕ(⋅) (and thusthe interleaver 304) that optimizes the performance of one-step decodingof the concatenated code for any given linear block code as the outercode. While the outer code can be any linear block code in general, inthis example, the outer code is assumed to be a CRC code. The sameprinciple can be extended to cover other types of outer codes. A flowdiagram for this procedure is illustrated in FIG. 7.

Step 700: a K×(K+K_(CRC)) systematic generator matrixG_(outer)=[I|P_(outer)] of the outer code is first obtained, where | andP_(outer) denote the identity matrix and the corresponding parity matrixof the outer code.

Step 702: Compute row and column permutation matrices, Φ_(r), and Φ_(c),which are determined such that

G′_(outer)

Φ_(r)G_(outer)Φ_(c) ^(T)

is an upper block-triangular matrix with exactly K columns being thoseof the identity matrix I. Let ϕ_(r): {1, 2, . . . , K}→{1, 2, . . . , K}and ϕ_(c): {1, 2, . . . , K+K_(CRC)}→{1, 2, . . . , K+K_(CRC)} be thecorresponding row and column permutation mappings of Φ_(r) and Φ_(c),respectively.

Step 704: Combine the column permutation mapping (I), and theinformation bit mapping b: {1, 2, . . . , K+K_(CRC)} {1, 2, . . . , N}of the inner polar code that maps the output of the interleaver to theinput of the polar (inner) encoder 306 to form the desired interleavingmapping 0=b∘ϕ_(c), where N denotes the code length of the inner polarcode.

A preferred embodiment is to use a CRC code as the outer code. Below isan illustration using an example of how the interleaving mapping thatimproves one-step decoding performance can be obtained. It should beknown by those skilled in the art that the design of the interleavingmapping need not be confined by the method illustrated. From thisexample, other design methods can be similarly derived to construct aninterleaver that re-locates some CRC bits to earlier positions in thesuccessive decoding process.

First, it is illustrated how the generating matrix of CRC code can beobtained from the CRC generating polynomial. Let g_(CRC)(D) denote thegenerating polynomial of the CRC code. For LTE downlink controlchannels, 16-bit CRC is generated via the generator polynomial:g_(CRC)(D)=D¹⁶+D¹²+D⁵+1. The ith row of the corresponding systematicgenerating matrix G_(outer)=[I|P_(outer)] that satisfiesuG_(outer)=x_(outer), where u and x_(outer) denote the data bit vectorand the CRC coded bit vector, respectively, can be obtained by taking along division of D^(K−i+1) by g_(CRC)(D), for each i=1, 2, . . . , K,where K denotes the number of data bits.

For example, for K=K_(CRC)=8 and g_(CRC)(D)=D⁸+D⁷+D⁴+D³+D+1, there is:

$\begin{matrix}{G_{outer} = \left\lbrack {\underset{I}{\underset{}{\begin{matrix}1 & 0 & 0 & 0 & 0 & 0 & 0 & 0 \\0 & 1 & 0 & 0 & 0 & 0 & 0 & 0 \\0 & 0 & 1 & 0 & 0 & 0 & 0 & 0 \\0 & 0 & 0 & 1 & 0 & 0 & 0 & 0 \\0 & 0 & 0 & 0 & 1 & 0 & 0 & 0 \\0 & 0 & 0 & 0 & 0 & 1 & 0 & 0 \\0 & 0 & 0 & 0 & 0 & 0 & 1 & 0 \\0 & 0 & 0 & 0 & 0 & 0 & 0 & 1\end{matrix}}\mspace{14mu}}\underset{P_{outer}}{\underset{}{\begin{matrix}0 & 0 & 0 & 0 & 1 & 0 & 1 & 1 \\1 & 1 & 0 & 0 & 1 & 0 & 0 & 0 \\0 & 1 & 1 & 0 & 0 & 1 & 0 & 0 \\0 & 0 & 1 & 1 & 0 & 0 & 1 & 0 \\0 & 0 & 0 & 1 & 1 & 0 & 0 & 1 \\1 & 1 & 0 & 0 & 0 & 0 & 0 & 1 \\1 & 0 & 1 & 0 & 1 & 1 & 0 & 1 \\1 & 0 & 0 & 1 & 1 & 0 & 1 & 1\end{matrix}}}} \right\rbrack} & (1)\end{matrix}$

Methods herein take into account the structure of the CRC outer codeduring the SCL decoding of the inner polar code. However, as shown inEq. (1), any of the parity bits computed based on P_(outer) may dependon any subsets of the information bits. For example, the parity bit thatcorresponds to the first column of P_(outer) is a function of theinformation bits mapped to the second, sixth, seventh, and eighth rowsof G_(outer). As a result, all the parity bits need to be placed at theend of the decoding process. Since SCL decoding is sequential in nature,it is desirable to have parity bits depend on earlier bit decisions sothat incorrect decision paths can be eliminated earlier. For the CRCouter code, it is desirable that CRC bit j depends only on bit decisionsthat are made prior to processing of the CRC bit j.

This can be achieved to some extent by permuting the rows and columns ofG_(outer)=[I|P_(outer)]. Specifically, it is possible to transform itinto G _(outer)=[I|P _(outer)], where P _(outer) is an upper blocktriangular matrix. In the above example, Eq. (1) can be transformed into

$\begin{matrix}{{{\overset{\_}{G}}_{outer} = \begin{bmatrix}1 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 1 & 1 & 1 & 0 & 0 & 0 & 0 & 0 \\0 & 1 & 0 & 0 & 0 & 0 & 0 & 0 & 1 & 1 & 0 & 1 & 0 & 1 & 0 & 1 \\0 & 0 & 1 & 0 & 0 & 0 & 0 & 0 & 0 & 1 & 0 & 0 & 1 & 0 & 1 & 0 \\0 & 0 & 0 & 1 & 0 & 0 & 0 & 0 & 0 & 0 & 1 & 1 & 0 & 1 & 0 & 0 \\0 & 0 & 0 & 0 & 1 & 0 & 0 & 0 & 0 & 0 & 1 & 1 & 0 & 0 & 0 & 1 \\0 & 0 & 0 & 0 & 0 & 1 & 0 & 0 & 0 & 0 & 0 & 1 & 1 & 1 & 1 & 1 \\0 & 0 & 0 & 0 & 0 & 0 & 1 & 0 & 0 & 0 & 0 & 0 & 1 & 1 & 0 & 1 \\0 & 0 & 0 & 0 & 0 & 0 & 0 & 1 & 0 & 0 & 0 & 0 & 0 & 1 & 1 & 1\end{bmatrix}},} & (2)\end{matrix}$

where the entries in bold are those of P _(outer), when the rows andcolumns are permuted, respectively, according to the followingpermutation mappings:

-   -   ϕ_(c)=[3 7 4 2 6 8 5 1 14 11 10 9 12 13 15 16], and    -   ϕ_(r)=[3 7 4 2 6 8 5 1].

In the above example, Eq. (2) can be further transformed into

$\begin{matrix}{{G_{outer}^{\prime} = \begin{bmatrix}1 & 0 & 1 & 0 & 1 & 0 & 0 & 1 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 \\0 & 1 & 1 & 0 & 1 & 0 & 0 & 0 & 0 & 1 & 0 & 0 & 0 & 1 & 0 & 1 \\0 & 0 & 0 & 1 & 1 & 0 & 0 & 0 & 0 & 0 & 0 & 1 & 0 & 0 & 1 & 0 \\0 & 0 & 0 & 0 & 0 & 1 & 0 & 1 & 0 & 1 & 0 & 0 & 0 & 1 & 0 & 0 \\0 & 0 & 0 & 0 & 0 & 0 & 1 & 1 & 0 & 1 & 0 & 0 & 0 & 0 & 0 & 1 \\0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 1 & 1 & 0 & 1 & 0 & 1 & 1 & 1 \\0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 1 & 1 & 0 & 1 & 0 & 1 \\0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 1 & 1 & 1 & 1\end{bmatrix}},} & (3)\end{matrix}$

where the entries in bold are those of P _(outer), when the columns arepermuted according to the permutation mapping:

-   -   ϕ_(c)=[3 7 14 4 11 2 6 10 8 9 5 12 1 13 15 16], which defines        the corresponding column permutation mapping ϕ_(c)(⋅). Note that        G′_(outer) is an upper block triangular matrix.

Given the information bit mapping b: {1, 2, . . . , K+K_(CRC)} {1, 2, .. . , N} for the inner polar code, the overall interleaving mapping isgiven by ϕ(k)=b(ϕ_(c)(k)) for k∈{1, 2, . . . , K+K_(CRC)}.

The interleaving mapping of this example enables the first parity bit,which corresponds to the third column of G′_(outer) and is a function ofonly the first and second information bits, to be checked immediatelyafter decisions are made for the first and second information bits.Checking of the first parity bit does not need to wait until decisionsfor all information bits have been made. As a result, the CRC checkingcan be done for the first parity bit early in the decoding process. Ifthe CRC check for the first parity bit fails, then decoding for thisparticular decision path can end. If the CRC check for the first paritybit passes, then decoding for this particular decision path continuesuntil the second parity bit is reached. A CRC check is then performedfor the second parity bit, and so on. If all decision paths are endeddue to failure to pass CRC check, the decoder can end the entiredecoding process and declare that an erred code block is detected. Inthis manner, the parity bits can be considered earlier in the decodingprocess to influence the decoding in a positive manner in terms ofreducing average decoding time.

The proposed designs, or other variant designs, include at least thefollowing features and benefits:

-   -   a. CRC checking can be done bit-by-bit for each individual CRC        bit. This is in contrast to existing methods where the entire        length-K_(CRC) vector of CRC bits are used in CRC checking;    -   b. The CRC checking can be performed during the SCL decoding.        This is in contrast to existing methods which performs CRC        checking only at the end of SCL decoding.

FIG. 8 is a schematic block diagram of a radio access node 800 accordingto some embodiments of the present disclosure. The radio access node 800may be, for example, a base station 202 or 206. As illustrated, theradio access node 800 includes a control system 802 that includes one ormore processors 804 (e.g., Central Processing Units (CPUs), ApplicationSpecific Integrated Circuits (ASICs), Field Programmable Gate Arrays(FPGAs), and/or the like), memory 806, and a network interface 808. Inaddition, the radio access node 800 includes one or more radio units 810that each includes one or more transmitters 812 and one or morereceivers 814 coupled to one or more antennas 816. In some embodiments,the radio unit(s) 810 is external to the control system 802 andconnected to the control system 802 via, e.g., a wired connection (e.g.,an optical cable). However, in some other embodiments, the radio unit(s)810 and potentially the antenna(s) 816 are integrated together with thecontrol system 802. The one or more processors 804 operate to provideone or more functions of a radio access node 800 as described herein. Insome embodiments, the function(s) are implemented in software that isstored, e.g., in the memory 806 and executed by the one or moreprocessors 804.

FIG. 9 is a schematic block diagram that illustrates a virtualizedembodiment of the radio access node 800 according to some embodiments ofthe present disclosure. This discussion is equally applicable to othertypes of network nodes. Further, other types of network nodes may havesimilar virtualized architectures.

As used herein, a “virtualized” radio access node is an implementationof the radio access node 800 in which at least a portion of thefunctionality of the radio access node 800 is implemented as a virtualcomponent(s) (e.g., via a virtual machine(s) executing on a physicalprocessing node(s) in a network(s)). As illustrated, in this example,the radio access node 800 includes the control system 802 that includesthe one or more processors 804 (e.g., CPUs, ASICs, FPGAs, and/or thelike), the memory 806, and the network interface 808 and the one or moreradio units 810 that each includes the one or more transmitters 812 andthe one or more receivers 814 coupled to the one or more antennas 816,as described above. The control system 802 is connected to the radiounit(s) 810 via, for example, an optical cable or the like. The controlsystem 802 is connected to one or more processing nodes 900 coupled toor included as part of a network(s) 902 via the network interface 808.Each processing node 900 includes one or more processors 904 (e.g.,CPUs, ASICs, FPGAs, and/or the like), memory 906, and a networkinterface 908.

In this example, functions 910 of the radio access node 800 describedherein are implemented at the one or more processing nodes 900 ordistributed across the control system 802 and the one or more processingnodes 900 in any desired manner. In some particular embodiments, some orall of the functions 910 of the radio access node 800 described hereinare implemented as virtual components executed by one or more virtualmachines implemented in a virtual environment(s) hosted by theprocessing node(s) 900. As will be appreciated by one of ordinary skillin the art, additional signaling or communication between the processingnode(s) 900 and the control system 802 is used in order to carry out atleast some of the desired functions 910. Notably, in some embodiments,the control system 802 may not be included, in which case the radiounit(s) 810 communicate directly with the processing node(s) 900 via anappropriate network interface(s).

In some embodiments, a computer program including instructions which,when executed by at least one processor, causes the at least oneprocessor to carry out the functionality of radio access node 800 or anode (e.g., a processing node 900) implementing one or more of thefunctions 910 of the radio access node 800 in a virtual environmentaccording to any of the embodiments described herein is provided. Insome embodiments, a carrier comprising the aforementioned computerprogram product is provided. The carrier is one of an electronic signal,an optical signal, a radio signal, or a computer readable storage medium(e.g., a non-transitory computer readable medium such as memory).

FIG. 10 is a schematic block diagram of the radio access node 800according to some other embodiments of the present disclosure. The radioaccess node 800 includes one or more modules 1000, each of which isimplemented in software. The module(s) 1000 provide the functionality ofthe radio access node 800 described herein. This discussion is equallyapplicable to the processing node 900 of FIG. 9 where the modules 1000may be implemented at one of the processing nodes 900 or distributedacross multiple processing nodes 900 and/or distributed across theprocessing node(s) 900 and the control system 802.

FIG. 11 is a schematic block diagram of a UE 212 according to someembodiments of the present disclosure. As illustrated, the UE 212includes one or more processors 1100 (e.g., CPUs, ASICs, FPGAs, and/orthe like), memory 1102, and one or more transceivers 1104 each includingone or more transmitters 1106 and one or more receivers 1108 coupled toone or more antennas 1110. In some embodiments, the functionality of theUE 212 described above may be fully or partially implemented in softwarethat is, e.g., stored in the memory 1102 and executed by theprocessor(s) 1100.

In some embodiments, a computer program including instructions which,when executed by at least one processor, causes the at least oneprocessor to carry out the functionality of the UE 212 according to anyof the embodiments described herein is provided. In some embodiments, acarrier comprising the aforementioned computer program product isprovided. The carrier is one of an electronic signal, an optical signal,a radio signal, or a computer readable storage medium (e.g., anon-transitory computer readable medium such as memory).

FIG. 12 is a schematic block diagram of the UE 212 according to someother embodiments of the present disclosure. The UE 212 includes one ormore modules 1200, each of which is implemented in software. Themodule(s) 1200 provide the functionality of the UE 212 described herein.

While processes in the figures may show a particular order of operationsperformed by certain embodiments of the present disclosure, it should beunderstood that such order is exemplary (e.g., alternative embodimentsmay perform the operations in a different order, combine certainoperations, overlap certain operations, etc.).

While the present disclosure has been described in terms of severalembodiments, those skilled in the art will recognize that the presentdisclosure is not limited to the embodiments described, can be practicedwith modification and alteration within the spirit and scope of theappended claims. The description is thus to be regarded as illustrativeinstead of limiting.

At least some of the following abbreviations may be used in thisdisclosure. If there is an inconsistency between abbreviations,preference should be given to how it is used above. If listed multipletimes below, the first listing should be preferred over any subsequentlisting(s).

-   -   3GPP Third Generation Partnership Project    -   5G Fifth Generation    -   ASIC Application Specific Integrated Circuit    -   CPU Central Processing Unit    -   CRC Cyclic Redundancy Check    -   eNB Enhanced or Evolved Node B    -   FPGA Field Programmable Gate Array    -   gNB New Radio Base Station    -   LDPC Low-Density Parity-Check    -   LLR Log-Likelihood Ratio    -   LTE Long Term Evolution    -   ML Maximum-Likelihood    -   MME Mobility Management Entity    -   MTC Machine-Type Communication    -   NR New Radio    -   P-GW Packet Data Network Gateway    -   RRH Remote Radio Head    -   SC Successive Cancellation    -   SCEF Service Capability Exposure Function    -   SCL Successive Cancellation List

Those skilled in the art will recognize improvements and modificationsto the embodiments of the present disclosure. All such improvements andmodifications are considered within the scope of the concepts disclosedherein.

REFERENCES

-   [1] E. Arikan, “Channel Polarization: A Method for Constructing    Capacity-Achieving Codes for Symmetric Binary-Input Memoryless    Channels,” IEEE Transactions on Information Theory, vol. 55, pp.    3051-3073, July 2009.-   [2] I. Tal and A. Vardy, “List Decoding of polar codes,” in    Proceedings of IEEE Symp. Inf. Theory, pp. 1-5, 2011.

What is claimed is:
 1. A method of operation of a radio node to performencoding of a plurality of data bits for transmission by the radio node,comprising: encoding a plurality of data bits using a linear encoder toprovide a first plurality of coded bits, the first plurality of codedbits comprising a plurality of parity bits and the plurality of databits, where the plurality of parity bits are a single parity check code;interleaving the first plurality of coded bits in accordance with aninterleaving mapping to provide a plurality of interleaved bits; andencoding the plurality of interleaved bits using a polar encoder toprovide a second plurality of coded bits to be transmitted by the radionode.
 2. The method of claim 1 wherein the interleaving mapping maps theplurality of interleaved bits to inputs of the polar encoder.
 3. Themethod of claim 1 wherein the plurality of interleaved bits is asequence of bits comprising the plurality of parity bits interleavedwith the plurality of data bits, and the interleaving mapping is suchthat at least one of the plurality of parity bits precedes at least oneof the plurality of data bits in the sequence of bits.
 4. The method ofclaim 1 wherein: the plurality of interleaved bits is a sequence of bitscomprising the plurality of parity bits interleaved with the pluralityof data bits; each parity bit of the plurality of parity bits is afunction of a respective subset of the plurality of data bits; and theinterleaving mapping is such that at least one of the plurality ofparity bits is at a position in the sequence of bits that is: (a) afterall of the subset of the plurality of data bits of which the at leastone of the plurality of parity bits is a function and (b) before a lastof the plurality of data bits within the sequence of bits.
 5. The methodof claim 1 wherein: the plurality of interleaved bits is a sequence ofbits comprising the plurality of parity bits interleaved with theplurality of data bits; each parity bit of the plurality of parity bitsis a function of a respective subset of the plurality of data bits; andthe interleaving mapping is such that at least one of the plurality ofparity bits is at a position in the sequence of bits that is: (a)immediately after a last of the subset of the plurality of data bits ofwhich the at least one of the plurality of parity bits is a functionwithin the sequence of bits and (b) before a last of the plurality ofdata bits within the sequence of bits.
 6. The method of claim 1 wherein:encoding the plurality of data bits using the linear encoder comprisesencoding the plurality of data bits in accordance with a generatormatrix G_(outer)=[I|P_(outer)], where I is an identity matrix of sizeK×K where K is the number of data bits in the plurality of data bits andP_(outer) is a parity matrix that defines each of the plurality ofparity bits as a function of a respective subset of the plurality ofdata bits; and the interleaving mapping is defined as ϕ=b∘φ_(c), where:b is a bit mapping that maps the plurality of interleaved bits to aplurality of non-frozen inputs of the polar encoder; and ϕ_(c) is acolumn permutation mapping of a column permutation matrix Φ_(c) that,together with a row permutation matrix Φ_(r), provide G′_(outer)

Φ_(r)G_(outer)Φ_(c) ^(T), where G′_(outer) is an upper block-triangularmatrix with exactly K being those of the identity matrix I.
 7. Themethod of claim 1 wherein the linear encoder is a Cyclic RedundancyCheck, CRC, encoder.
 8. A radio node for performing encoding of aplurality of data bits for transmission by the radio node, the radionode comprising: a transmitter; and at least one processor operable to:encode a plurality of data bits using a linear encoder to provide afirst plurality of coded bits, the first plurality of coded bitscomprising a plurality of parity bits and the plurality of data bits,where the plurality of parity bits are a single parity check code;interleave the first plurality of coded bits in accordance with aninterleaving mapping to provide a plurality of interleaved bits; andencode the plurality of interleaved bits and one or more frozen bitsusing a polar encoder to provide a second plurality of coded bits to betransmitted by the radio node.
 9. The radio node of claim 8 wherein theinterleaving mapping maps the plurality of interleaved bits to inputs ofthe polar encoder.
 10. The radio node of claim 8 wherein the pluralityof interleaved bits is a sequence of bits comprising the plurality ofparity bits interleaved with the plurality of data bits, and theinterleaving mapping is such that at least one of the plurality ofparity bits precedes at least one of the plurality of data bits in thesequence of bits.
 11. The radio node of claim 8 wherein: the pluralityof interleaved bits is a sequence of bits comprising the plurality ofparity bits interleaved with the plurality of data bits; each parity bitof the plurality of parity bits is a function of a respective subset ofthe plurality of data bits; and the interleaving mapping is such that atleast one of the plurality of parity bits is at a position in thesequence of bits that is: (a) after all of the subset of the pluralityof data bits of which the at least one of the plurality of parity bitsis a function and (b) before a last of the plurality of data bits withinthe sequence of bits.
 12. The radio node of claim 8 wherein: theplurality of interleaved bits is a sequence of bits comprising theplurality of parity bits interleaved with the plurality of data bits;each parity bit of the plurality of parity bits is a function of arespective subset of the plurality of data bits; and the interleavingmapping is such that at least one of the plurality of parity bits is ata position in the sequence of bits that is: (a) immediately after a lastof the subset of the plurality of data bits of which the at least one ofthe plurality of parity bits is a function within the sequence of bitsand (b) before a last of the plurality of data bits within the sequenceof bits.
 13. The radio node of claim 8 wherein: in order to encode theplurality of data bits using the linear encoder, the radio node isfurther operable to encode the plurality of data bits in accordance witha generator matrix G_(outer)=[I|P_(outer)], where I is an identitymatrix of size K×K where K is the number of data bits in the pluralityof data bits and P_(outer) is a parity matrix that defines each of theplurality of parity bits as a function of a respective subset of theplurality of data bits; and the interleaving mapping is defined asϕ=b∘φ_(c), where: b is a bit mapping that maps the plurality ofinterleaved bits to a plurality of non-frozen inputs of the polarencoder; and ϕ_(c) is a column permutation mapping of a columnpermutation matrix Φ_(c) that, together with a row permutation matrixΦ_(r), provide G′_(outer)

Φ_(r)G_(outer)Φ_(c) ^(T), where G′_(outer) is an upper block-triangularmatrix with exactly K being those of the identity matrix I.
 14. Theradio node of claim 8 wherein the linear encoder is a Cyclic RedundancyCheck, CRC, encoder.
 15. A method of operation of a radio node toperform decoding of a plurality of coded bits received by the radionode, comprising: decoding a plurality of coded data bits using a polardecoder to provide a plurality of decoded bits, the plurality of decodedbits comprising a plurality of parity bits interleaved with a pluralityof data bits, where the plurality of parity bits are a single paritycheck code; and deinterleaving the plurality of decoded bits inaccordance with an interleaving mapping to thereby provide the pluralityof parity bits and the plurality of data bits.
 16. The method of claim15 wherein decoding the plurality of coded bits comprises decoding aplurality of input Log-Likelihood Ratios, LLRs, of the plurality ofcoded bits using a modified Successive Cancellation List, SCL, polardecoder, wherein: the plurality of coded bits is a plurality of polarencoded bits that result from a polar encoding of the plurality ofinterleaved bits comprising the plurality of data bits and the pluralityof parity bits that are interleaved with the plurality of data bits inaccordance with the interleaving mapping; and the modified SCL polardecoder is a SCL polar decoder that takes into account the interleavingmapping.
 17. The method of claim 15 wherein the plurality of interleavedbits is a sequence of bits comprising the plurality of parity bitsinterleaved with the plurality of data bits, and the interleavingmapping is such that at least one of the plurality of parity bitsprecedes at least one of the plurality of data bits in the sequence ofbits.
 18. The method of claim 15 wherein: the plurality of interleavedbits is a sequence of bits comprising the plurality of parity bitsinterleaved with the plurality of data bits; each parity bit of theplurality of parity bits is a function of a respective subset of theplurality of data bits; and the interleaving mapping is such that atleast one of the plurality of parity bits is at a position in thesequence of bits that is: (a) after all of the subset of the pluralityof data bits of which the at least one of the plurality of parity bitsis a function and (b) before a last of the plurality of data bits withinthe sequence of bits.
 19. The method of claim 15 wherein: the pluralityof interleaved bits is a sequence of bits comprising the plurality ofparity bits interleaved with the plurality of data bits; each parity bitof the plurality of parity bits is a function of a respective subset ofthe plurality of data bits; and the interleaving mapping is such that atleast one of the plurality of parity bits is at a position in thesequence of bits that is: (a) immediately after a last of the subset ofthe plurality of data bits of which the at least one of the plurality ofparity bits is a function within the sequence of bits and (b) before alast of the plurality of data bits within the sequence of bits.
 20. Themethod of claim 15 wherein the plurality of data bits and the pluralityof parity bits are a result of Cyclic Redundancy Check, CRC, encoding ofthe plurality of data bits.
 21. A radio node to perform decoding of aplurality of coded bits received by the radio node, comprising: atransmitter; and at least one processor operable to: decode a pluralityof coded data bits using a polar decoder to provide a plurality ofdecoded bits, the plurality of decoded bits comprising a plurality ofparity bits interleaved with a plurality of data bits, where theplurality of parity bits are a single parity check code; anddeinterleave the plurality of decoded bits in accordance with aninterleaving mapping to thereby provide the plurality of parity bits andthe plurality of data bits.
 22. The radio node of claim 21 wherein, inorder to decode the plurality of coded bits, the at least one processoris further operable to decode a plurality of input Log-LikelihoodRatios, LLRs, of the plurality of coded bits using a modified SuccessiveCancellation List, SCL, polar decoder, wherein: the plurality of codedbits is a plurality of polar encoded bits that result from a polarencoding of the plurality of interleaved bits comprising the pluralityof data bits and the plurality of parity bits that are interleaved withthe plurality of data bits in accordance with the interleaving mapping;and the modified SCL polar decoder is a SCL polar decoder that takesinto account the interleaving mapping.
 23. The radio node of claim 21wherein the plurality of interleaved bits is a sequence of bitscomprising the plurality of parity bits interleaved with the pluralityof data bits, and the interleaving mapping is such that at least one ofthe plurality of parity bits precedes at least one of the plurality ofdata bits in the sequence of bits.
 24. The radio node of claim 21wherein: the plurality of interleaved bits is a sequence of bitscomprising the plurality of parity bits interleaved with the pluralityof data bits; each parity bit of the plurality of parity bits is afunction of a respective subset of the plurality of data bits; and theinterleaving mapping is such that at least one of the plurality ofparity bits is at a position in the sequence of bits that is: (a) afterall of the subset of the plurality of data bits of which the at leastone of the plurality of parity bits is a function and (b) before a lastof the plurality of data bits within the sequence of bits.
 25. The radionode of claim 21 wherein: the plurality of interleaved bits is asequence of bits comprising the plurality of parity bits interleavedwith the plurality of data bits; each parity bit of the plurality ofparity bits is a function of a respective subset of the plurality ofdata bits; and the interleaving mapping is such that at least one of theplurality of parity bits is at a position in the sequence of bits thatis: (a) immediately after a last of the subset of the plurality of databits of which the at least one of the plurality of parity bits is afunction within the sequence of bits and (b) before a last of theplurality of data bits within the sequence of bits.
 26. The radio nodeof claim 21 wherein the plurality of data bits and the plurality ofparity bits are a result of Cyclic Redundancy Check, CRC, encoding ofthe plurality of data bits.